1) Field of the Invention
Embodiments of the present invention relate to a method for low power accessing a phase change memory device.
2) Description of Related Art
As is known, phase change memories are formed by memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element and a selection element. A memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum between completely amorphous and completely crystalline states.
Typical materials suitable for the phase change region of the memory elements include various chalcogenide elements. The state of the phase change material is non-volatile, absent application of excess temperatures, such as those in excess of 150° C., for extended times. Therefore, when a memory element is set in either a crystalline semi-crystalline, amorphous, or semi-amorphous state, each of them associated with a different resistance value, that value is retained until reprogrammed, even if power is removed. Thus, data can be stored in the memory elements in form of respective resistance levels associated to different phases of the phase-change material.
Selection elements may be formed according to different technologies, for example they can be implemented by diodes, by MOS transistors or bipolar transistors.
With reference to FIG. 1, a phase-change memory device 1 comprises an array 2 of PCM cells 3, arranged in rows and columns and connected to a column decoder 5 and a row decoder stage 6; a write/read selector 8 connects the column decoder 5 to either a sense stage 9 or a write stage 10, as controlled by control signals (not shown) whose values depend on the operative phase of the phase-change memory device 1.
FIG. 1 also illustrates one exemplar PCM cell 3 of the array 1. All PCM cells 3 are identical and include a phase-change memory element 11 and a cell selector 12 coupled in series. In FIG. 1, the phase-change memory element 11 is illustrated as a resistor having variable resistance level. In the embodiment shown, the cell selector 12 is a PNP bipolar transistor controlled to allow current to flow through the respective phase-change memory element 11 during reading and programming/verifying operations. Each phase-change memory element 11 is directly connected to a respective bit line 15 and is connected to a respective word line 16 through the cell selector 12.
Groups of PCM cells 3 are selectively addressable by the column decoder 5 and the row decoder stage 6. In particular the row decoder stage 6 connects selected word lines 16 to a low voltage (as close as possible to Vss) and unselected word lines 16 to a relatively high voltage (typically 1.3 V during reading and 3.8 V during writing).
FIG. 2 shows a more detailed diagram of the memory array 2. In the embodiment, the memory array 2 is divided into a plurality of tiles 20 (only two whereof are shown in FIG. 2, for sake of clarity), comprising each e.g. 1024 word lines. Each tile 20 is connected to an own local row decoder 21 belonging to the row decoder stage 6. A global row decoder 22 is formed farer from the tiles 20 and generates address signals for the local row decoders 21. Each bitline 15, when deselected, is connected a low voltage Vss through an own pull-down transistor 23 controlled by the respective local row decoder 21.
As shown in FIG. 3, each tile 20 may store a plurality of data for each wordline 16. In the example shown, two data (D0, D1) are stored for each wordline 16, and each datum is stored in n cells 3, connected to n bitlines 15. Specifically, in the example, bitlines BL<0>-BL<n−1> are associated to D0 and bitlines BL<n>-BL<2n1> are associated to D1 of each wordline. Let's assume, for simplicity, that each cell 3 stores a bit; this means that bitlines BL<0>-BL<n−1> are associated to bit(0)-bit(n−1) of D0 and bitlines BL<n>-BL<2n−1> are associated to bit(0)-bit(n−1) of D1.
In such a situation, parallel writing of D0, D1 on a wordline may require a high write current and cause a high voltage drop on the selected wordline. In fact, writing of a bit is carried out by supplying a write current to the selected bitline 15; this current, divided by the gain of the accessed cell selector 12, flows through the selected wordline 16. Since the gain of the cell selectors 12 is low (of the order of 2-3), the current flowing on the selected wordline is a non-negligible fraction of the write current, and thus is quite high. This wordline current causes a voltage drop on the wordline 16 which depends on the position of the selected cell; thus the voltage on the control terminal of the addressed selector is equal to the sum of the driver voltage Vdr fed by the local row decoder 21 to selected wordline 16 plus the voltage drop on the selected wordline 16.
If both data are to be written simultaneously, the wordline currents on the selected wordline are summed up, further increasing the voltage drop, as below discussed.
Let's consider for example, the simultaneous writing of bit(0) of both D0 and D1 on wordline WL<0>, as shown in FIG. 3. Thus, writing currents are supplied to bitlines BL<0> and BL<n>.
In such a situation, the voltage on the control terminal of cell 30 connected to bitline BL<0> is equal to driver voltage Vdr, since this cell is very close to the local row decoder 21, while the voltage V1 on the control terminal of cell 31 connected to bitline BL<n> is:V1=Vdr+½R*Iw/β
wherein R is the resistence of the wordline 16, Iw is the writing current supplied to the selected bitline 15 and β is the gain of the transistor forming the cell selector 12.
Let's now consider the simultaneous writing of bit(n−1) of both D0 and D1, as shown in FIG. 4. In such a situation, the current flowing on wordline WL<0> from bitline BL<n−1> to the local row decoder 21 is the sum of the currents injected by both bitlines BL<n−1> and BL<2n−1> divided by the gain β (2Iw/β). In such a situation, the voltage V2 on the control terminal of cell 32 connected to bitline BL<n−1> is due the driver voltage Vdr plus the voltage drop across the portion of the wordline comprised between the local row decoder and bitline BL<n−1>, thus:V2=Vdr+½R(2Iw/β)=Vdr+R*Iw/β. 
The voltage V3 on the control terminal of cell 33 connected to bitline BL<2n−1> is equal to V2 plus the voltage drop across the portion of the selected wordline WL<0> comprised between bitline BL<2n−1> and bitline BL<n−1>, due to current Iw/β. Thus:V3=Vdr+R*Iw/β+½R*Iw/β=Vdr+(3/2)R*Iw/β. 
Thus, in the just discussed worst case, where the cells 3 to be written lie at the farthest positions from the local row decoder 21 for each datum, the current flowing along the selected wordline may generate a very high voltage drop on the selected wordline.
Therefore, parallel writing of two data may cause an inacceptable dissipation in the memory array, preventing in practice the parallel writing of more than one datum.
The object of the invention is thus to solve the problem outlined above, and in particular to allow parallel writing of more than one datum each time.
According to embodiments of the present invention, there are provided methods for accessing a phase change memory device and a phase change memory device.